CP2130
S
INGLE
- C
H IP
USB-
T O
- S P I B
R ID GE
Single-Chip USB-to-SPI Bridge
clock; no external crystal required
Integrated USB transceiver; no external resistors
required
Integrated 348 Byte one-time programmable ROM for
product customization
On-chip power-on reset circuit
On-chip voltage regulator: 3.45 V output
Uses USB Bulk Mode transactions for high throughput
- Configurable priority for reads and writes
Integrated
SPI Controller
or 4-wire master mode operation
Configurable clock rate
- 12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz,
187.5 kHz, 93.75 kHz
Clock phase and polarity control
Chip select mode and toggle
Programmable SPI delay (post-assert, inter-byte, pre-
deassert)
3
USB Peripheral Function Controller
USB
11 Configurable GPIO Pins with Alternate Functions
as inputs, open-drain outputs, or push-pull
outputs
Up to 11 chip select outputs
Ready-to-read pin allows for external signal to trigger
SPI read operations
Ability to count edges or pulses using the Event Counter
Up to 11 USB remote wakeup sources
SPI activity indication (toggles to indicate SPI activity)
Configurable clock output (93.75 kHz to 24 MHz)
Usable
Specification 2.0 compliant; full-speed (12 Mbps)
USB suspend states supported and indicated via
suspend output pins
USB Interface
8
®
, 7
®
, Vista
®
, and XP
®
Open access to interface specification
Windows
Windows Libraries
APIs
for quick application development
Windows
8
®
,
7
®
,
Vista
®
,
and
XP
®
(SP2 &
Supports
Supply Voltage
powered (regulator disabled): 3.0 to 3.6 V
Self powered (regulator enabled): 3.0 to 5.25 V
USB bus powered: 4.0 to 5.25 V
I/O voltage: 1.8 V to V
DD
Self
SP3)
Packages
RoHS-compliant
24-QFN package (4x4 mm)
Ordering Part Numbers
CP2130-F01-GM
Temperature Range: –40 to +85 °C
CP2130
Connect to VBUS
or External Supply
USB
Connector
VBUS
D+
D-
GND
VREGIN
VDD
Voltage
Regulator
48 MHz
Oscillator
MISO
SPI Controller
MOSI
SCK
To SPI
Slave
Devices
GND
VBUS
D+
D-
USB Interface
Full-Speed
12 Mbps
Transceiver
Peripheral
Function
Controller
Multi-Function
Signals
GPIO
SPI Chip Select
SPI ReadyToRead
SPI Event Counter
Clock Output
SPI Activity
USB Suspend
Remote Wakeup
GPIO.0_CS0
GPIO.1_CS1
GPIO.2_CS2
GPIO.3_CS3_RTR
GPIO.4_CS4_EVTCNTR
GPIO.5_CS5_CLKOUT
GPIO.6_CS6
GPIO.7_CS7
GPIO.8_CS8_SPIACT
GPIO.9_CS9_SUSPEND
GPIO.10_CS10_SUSPEND
Hardware Reset
RESET
VPP
348 Byte PROM
(Product Customization)
Multi-
Function
Signals to
External
Circuitry
Logic Level
Supply
(1.8 V to VDD)
VIO
I/O Power and Logic Levels
Figure 1. Example System Diagram
Rev. 0.7 1/14
Copyright © 2014 by Silicon Laboratories
CP2130
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
CP2130
2
Rev. 0.7
CP2130
T
ABLE
Section
OF
C
ONTENTS
Page
1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. USB Function Controller and Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Serial Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1. GPIO.3—Ready-to-Read (RTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. GPIO.4—Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3. GPIO.5—Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4. GPIO.8—SPI Activity Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5. GPIO.9-10—SUSPEND and SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6. USB Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7. GPIO State During USB Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. One-Time Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
8. CP2130 Interface Specification and Windows Interface DLL . . . . . . . . . . . . . . . . . . . . .20
9. Relevant Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11. QFN-24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Rev. 0.7
3
CP2130
1. System Overview
The CP2130 is a highly-integrated USB-to-SPI bridge controller providing a simple solution for bridging a Universal
Serial Bus (USB) host to a Serial Peripheral Interface (SPI) bus using a minimum of components and PCB space.
The CP2130 includes a USB 2.0 full-speed controller, USB transceiver, oscillator, one-time programmable (OTP)
ROM, and a SPI controller in a compact 4 x 4 mm QFN24 package (sometimes called “MLF” or “MLP”).
The on-chip, OTP ROM provides the option to customize the USB Vendor ID, Product ID, Manufacturer String,
Product Description String, Power Descriptor, Device Release Number, Device Serial Number, and GPIO
configuration as desired for OEM applications.
The CP2130 uses a Silicon Labs vendor-specific USB protocol using control and bulk transfers which is supported
by most operating systems through the use of generic USB drivers and interface libraries. A custom driver typically
does not need to be developed for this device. Windows applications communicate with the CP2130 through a
Windows DLL which is provided by Silicon Labs that communicates with the Microsoft WinUSB driver via a
WinUSB DLL. The interface specification for the CP2130 is also available to enable development of an API for any
operating system that supports control and bulk transfers over USB.
The CP2130 SPI implements the standard signals, including SCK, MISO, MOSI, CS, as well as a ready-to-read
(RTR) hardware handshaking input, so existing system firmware does not need to be modified. The SPI
capabilities of the CP2130 include fixed SPI clock rates ranging from 93.75 kHz to 12 MHz, configurable clock
phase, configurable clock polarity, adjustable SPI delays, and up to 11 configurable chip select signals.
Any of the multi-purpose pins not used as chip select signals may instead be used as GPIO signals that are user-
defined. The GPIO signals may also be configured to initiate a USB remote wakeup event on GPIO state change,
which allows the CP2130 to wake a USB host from sleep mode. Eight of the GPIO signals support alternate
features including ready-to-read (RTR) handshaking, a configurable event counter, a configurable clock output
(93.75 kHz to 24 MHz), SPI activity LED toggle, and USB suspend indicators. Support for I/O interface voltages
down to 1.8 V is provided via a V
IO
pin.
An evaluation kit for the CP2130 (Part Number: CP2130EK) is available. It includes a CP2130-based USB-to-SPI
evaluation board with SPI slave devices such as an EEPROM and ADC as well as connections for an external
CP2400 LCD controller EVB and SPI monitor. The kit also includes a Windows DLL and test application, USB
cables, and full documentation. See
www.silabs.com
for the latest application notes and product support
information for the CP2130. Contact a Silicon Labs sales representatives or go to
www.silabs.com
to order the
CP2130 Evaluation Kit.
4
Rev. 0.7
CP2130
2. Electrical Characteristics
Table 1. Global DC Electrical Characteristics
V
DD
= 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
Digital Supply Voltage
Digital Port I/O Supply
Voltage
Specified Operating
Temperature Range
Thermal Resistance
1
Supply Current
Symbol
V
DD
V
IO
T
A
θ
JA
Test Condition
Min
3.0
1.8
–40
—
Typ
—
—
—
28
170
170
210
14.4
13.8
14.1
17.8
16.6
17.1
200
Max
3.6
V
DD
+85
—
360
290
330
18.8
18.1
18.4
23.2
21.7
22.2
230
Unit
V
V
°C
°C/W
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
Bus Powered; Regulator enabled
USB Suspended
2
Self Powered; Regulator disabled; V
DD
= 3.0 V
Self Powered; Regulator disabled; V
DD
= 3.3 V
Bus Powered; Regulator enabled
USB Normal; SPI Idle
2
I
REGIN
Self Powered; Regulator disabled; V
DD
= 3.0 V
Self Powered; Regulator disabled; V
DD
= 3.3 V
Bus Powered; Regulator enabled
USB Normal; SPI
Active
2
USB Pull-up
3
I
PU
Self Powered; Regulator disabled; V
DD
= 3.0 V
Self Powered; Regulator disabled; V
DD
= 3.3 V
—
—
—
—
—
—
—
—
—
—
Notes:
1.
Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
2.
USB Pull-up current should be added for total supply current. USB normal and suspended supply current is current
flowing into V
REGIN
. USB normal and suspended supply current is guaranteed by characterization.
3.
The USB Pull-up supply current values are calculated values based on USB specifications. USB Pull-up supply current
is current flowing from VDD to GND through USB pull-down/pull-up resistors on D+ and D-.
Rev. 0.7
5
